1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same; and, more particularly, to a layout of a semiconductor memory device having a dummy cell and a method of controlling capacitance of the dummy cell.
2. Description of the Related Art
In a semiconductor memory, data is stored in a memory cell and is selectively read from the memory cell. The data read from the memory cell is transferred to a sense amplifier through a bit line. Then, the sense amplifier amplifies the data and determines a logic level of associated bit lines. Therefore, the bit line and the sense amplifier are essential elements for processing the data of the semiconductor memory device.
FIG. 1 is a plan view illustrating a layout of a semiconductor memory device having a conventional dummy cell.
Referring to FIG. 1, an edge portion of a memory device includes a dummy cell array (Array 00) which corresponds to a main cell array (Array 01), wherein a cell size and the number of cells per dummy bit line in the dummy cell array (Array 00) are identical to those in the main cell array (Array 01). The dummy cell array (Array 00) is used as a reference to detect the data stored in the main cell array (Array 01).
The semiconductor memory device having a dummy cell includes a plurality of memory cells 12, a plurality of sense amplifiers 18 and a plurality of dummy cells 20. The plurality of memory cells 12 for storing data are arranged in a row direction, i.e., x-axis, and a column direction, i.e., y-axis, on a semiconductor substrate 10. A plurality of bit lines 14 which extend in the row direction are perpendicularly intersected with a plurality of word lines 16 extending in the column direction. The plurality of sense amplifiers 18 connected to the plurality of bit lines 14 are arranged in the column direction with respect to the semiconductor substrate. That is, the plurality of bit lines 14 are connected to one end of each plurality of sense amplifiers 18 and are extended in the row direction.
The plurality of dummy cells 20 are connected to a plurality of dummy bit lines 22 and are extended in an opposite direction to the plurality of bit lines 14, wherein the plurality of sense amplifiers 18 are disposed between the plurality of dummy bit lines 22 and the plurality of bit lines 14. Herein, the number of memory cells 12 is identical to the number of dummy cells 20. Meanwhile, the dummy cell array (Array 00) occupies a predetermined area in the edge portion of the memory device. In order to reduce the occupation area of the dummy cell array (Array 00), various attempts have been made. For example, it is possible to arrange a pair of neighboring dummy cells in the dummy cell array (Array 00) as illustrated in FIG. 1. However, despite various efforts, dummy cell arrays (e.g. Array 00) typically occupy more than about 1.5% of the total area of a memory device.
Accordingly, a more efficient use of space on a semiconductor substrate for a memory device is desired.